XG836 Datasheet

(Version 2.0: 2018-7-1)

Catalogue

1. Device Overview... PAGEREF _Toc296679910 \h 3

2. Features. PAGEREF _Toc296679911 \h 3

3. Pin Assignment.. PAGEREF _Toc296679912 \h 5

3.1 Pin Description.. PAGEREF _Toc296679913 \h 6

3.2 PAD Assignment. PAGEREF _Toc296679914 \h 10

4. Functional Block Diagram... PAGEREF _Toc296679915 \h 12

5. Memory.. PAGEREF _Toc296679916 \h 13

5.1 Program Memory.. PAGEREF _Toc296679917 \h 13

5.2 Data Memory.. PAGEREF _Toc296679918 \h 13

5.3 Registers. PAGEREF _Toc296679919 \h 13

5.4 Register Table. PAGEREF _Toc296679920 \h 14

5.5 Registers description.. PAGEREF _Toc296679921 \h 16

6. System Clock and Options. PAGEREF _Toc296679922 \h 32

6.1 Oscillator.. PAGEREF _Toc296679923 \h 32

6.2 Crystal Oscillator.. PAGEREF _Toc296679924 \h 32

6.3 Low Frequency Crystal Oscillator.. PAGEREF _Toc296679925 \h 33

6.4 External RC Oscillator.. PAGEREF _Toc296679926 \h 33

6.5 Internal RC Oscillator.. PAGEREF _Toc296679927 \h 34

6.6 External Clock.. PAGEREF _Toc296679928 \h 34

7. System Control and Reset.. PAGEREF _Toc296679929 \h 35

7.1 Reset source. PAGEREF _Toc296679930 \h 35

8. Interrupt.. PAGEREF _Toc296679931 \h 36

8.1 Interrupt Vector.. PAGEREF _Toc296679932 \h 37

9. External Interrupt. PAGEREF _Toc296679933 \h 37

10. I/O Ports. PAGEREF _Toc296679934 \h 37

11. TIMER0 Module.. PAGEREF _Toc296679935 \h 38

12. SPI. PAGEREF _Toc296679936 \h 39

12.1 SPI Function Description.. PAGEREF _Toc296679937 \h 41

13. TIMER 1. PAGEREF _Toc296679938 \h 43

13.1 Overview... PAGEREF _Toc296679939 \h 43

13.2 Function Description.. PAGEREF _Toc296679940 \h 43

14. Analog to Digital Converter（A/D）.... PAGEREF _Toc296679941 \h 44

15. Digital to Analog Converter（D/A）.... PAGEREF _Toc296679942 \h 45

16. Asynchronous Serial I/O -UART.. PAGEREF _Toc296679943 \h 45

17. Electrical Characteristics. PAGEREF _Toc296679944 \h 46

17.1 Absolute Maximum Ratings. PAGEREF _Toc296679945 \h 46

17.2 Electrical Characteristics. PAGEREF _Toc296679946 \h 46

1. Device Overview

XG836 is an 8-bit high performance, low cost MCU which bases on RISC architecture. It is easy to use to deal with analog signal, for example, measurement applications with sensor. The XG836 has an embedded 10-bit analog to digital converter (ADC) with 16 channels, two pulse width modulators (PWM) and one 8-bit digital to analog converter (DAC). It also improved some internal characteristics, such as Halt Function, Wake-up Function, Oscillator Selection, and Programmable Frequency Prescaler. So, XG836 is very flexible for use, and just need least extra parts for cutting down the cost. For these advantages and good characteristics, such as Integrated A/D, Integrated D/A, Integrated PWM, low cost, high performance, flexible Input/Output, and low price, XG836 is very suitable for applications such as Sensor signal process, Motor drive, Industry control, Consumed product, and subsystem controller etc.

XG836 uses Reduced Instruction Set, and it has 256 bytes RAM, the user can easily visit the ROM and RAM but no need to change program page. The special function registers have same addressing mode with RAM

XG836 is One-Time Programmable (OTP), and user’s program can be easily and effectively emulated by our emulator. It provides an effective way for users to develop their program.

2. Features

· High performance, low cost, 8-bit MCU

· Advanced RISC architecture

-           59 instructions – most of the instructions are executed within one single instruction cycle（Fosc/2）

· Peripheral Features

-          One 8-bit timer with frequency prescaler

-          One 8-bit pulse width comparator with frequency prescaler

-          Watch dog with independent oscillator

-          One external interrupt

-          One Timer with frequency prescaler and interrupt function.

-          Embedded crystal and RC oscillator

-          Program interfaces and code protection

-          Low voltage reset（LVR）

-          15 I/O ports (P6、P7、P9、PA) with wake-up function

-          Two channels of PWM

-          10-bit ADC with 15 channels

-          8-bit DAC with one channel

-          A set of UART interface

-          Two sets of SPI interface

· Special Microcontroller Features

-          Power on reset and power off detect

-          Embedded, calibrated RC oscillator

-          6 hardware interrupt sources (external and internal)

-          8 levels stack

-          Two sleep modes, halt and sleep to get low consumption

-          Instructions are 16-bit，can visit all registers, RAM , ROM and no need to change program page

-          Table read function

-          Direct addressing and indirect addressing

-          Bit oriented instructions

· Memory

-          4K * 16bits    OTP ROM

-          256 * 8bits     RAM

-          128 * 8bits     Special function registers

· I/O and package

-          44 universal I/O ports

-          There are two more inputs when use internal RC oscillator

· Ambient operating temperature:  0 ~ 70°C

· Operating voltage range:  2.3 ~ 5.5V

· Operating Frequency range

1.       Crystal mode: DC~20MHz at 5V,  DC~8MHz at 3V,

2.       RC oscillator mode: 3~20MHz at 5V, 3~8MHz at 3V,

· Supply current of XG836 at 6MHz, 5V, 25°C

1.       Normal Mode:

It depends on the level of the LDO,

when LDO=3volt, the operating current <1.5mA (no load and transition on all I/Os).

2.       Sleep Mode:

< 4.5uA, when LDO on

< 1.5uA, when LDO off

3. Pin Assignment

Figure 3.1 Pin assignment

3.1 Pin Description

Note: I = Input       O = Output            I/O = Input/Output        P = Power

         - = not use          TTL = TTL Input   ST = Schmitt Input

3.2 PAD Assignment

Figure 3.2 Pad Assignment

          Unit:μm       Note: the underlay must be connected to GND

4. Functional Block Diagram

Figure 4.1 Functional Blocks

5. Memory

There are two main parts of memory space in XG836: Data memory and Program memory. And, XG836 has registers for special operation to those peripheral. Data memory have unified addresses with registers, but be separated from program memory.

5.1 Program Memory 

XG836 has embedded 4K * 16bit OTP (One Time Programmable) ROM. The reset vector is 0XFFF, the hardware interrupt vector is 0X001, and software interrupt vector is 0X002.

5.2 Data Memory

XG836 has 256 * 8bits RAM as data memory, it has two addressing modes: Direct Addressing and Indirect Addressing through R0.

5.3 Registers

128 * 8bits special registers doesn’t have continuous addresses. The result is unknown to read or write to those undefined addresses.

Special registers can only be visited by direct addressing.

5.4 Register Table

5.5 Registers description

Note:   ·R: Readable,  W: Writable, C: can be cleared

·RESE: Reset status

·U: Unchanged

A (Accumulator)

Internal data transfer, or instruction operand holding. It can’t be addressed.

INDF (Indirect address register) (Address: 0x100)

INDF is not a physical register. It is used for indirect addressing. Any instruction using R0 actually accesses the register pointed by FSR. While user reads data from INDF, the CPU gets data from the Data Memory at the address stored in FSR. While user writes the data into INDF, CPU actually saved the data into Data Memory at the address stored in FSR

TCC (Timer Register) (Address: 0x101)

This register is a 8-bit timer, can be read or written by program. It used to take count of internal clock. It has a programmable frequency prescaler（256 scale most）.

PCL (Program counter) and Stack (Address: 0x102)

R2 and hardware stack are 16 bits wide.

Generates 4096*16 on-chip ROM addresses to the relative programming instruction codes.

All bits of R2 are set to “1” as a RESET condition occurs.

• “ADD R2, A” allows relative address be loaded to current PC. Meanwhile, the high 8-bits of PC will be cleared.

•Any instruction that will change R2 (e.g. “ADD R2, A”, “MOV R2, A”, “BC R2, 6” etc, except “TBL”), will cause the higher 8-bits of PC to be cleared. Thus, the computed jump is limited to the first 256 locations of any program page.

• “TBL” allows the relative address be loaded to current PC (R2 + A→R2), and the higher 8-bits of  PC remains. Thus, the computed jump can be on any location of one program page.

• All instructions are executed within one instruction cycle(fclk/2) except for the instruction that would change the content of R2.

STATUS (Status Register) (Address: 0x103)

Status register contains the status of ALU calculation result and reset.

Just like the other registers, status register can be used as the destination operand of any instruction. If status register is used as destination operand, and the operation result affects either Z, DC, or C, then writing on Z, DC or C is prohibited. Setting or Clearing Z, DC, C depends on the logic module of the device.

Besides, T and P are un-writable. Thus, user may get an unexpected result if the status register is used as a destination operand.

Therefore if you want to change the content of the status register, we recommend you to use the bit oriented instructions (BC, BS), half-byte exchange instruction (SWAP), or move instruction (MOV R, A), because these instructions won’t affect Z, C, or DC.

GP: General purpose read-write bit.

T:   Time out flag

1: Power-on reset, SLEP instruction or WDTC instruction executed

0: A Watch Dog Timer time-out occurred

P:   Power down flag

1: Power-on reset or WDTC instruction executed

0: SLEP instruction executed

Z:  Zero flag

1: The result of arithmetic or Boolean calculation is zero

0: The result of arithmetic or Boolean calculation is not zero

DC: Digit carry/borrow flag（ADD，SUB instructions）

       1: There is a carry out from the 4^th bit of result

       0: No carry out from the 4^th bit of result

C:  carry/borrow flag（ADD，SUB instructions）

       1: There is a carry out from the most significant bit of result

       0: No carry out from the most significant bit of result

Notes: The most or least significant bit of original register will be load to C after executing RLC and RRC instruction

FSR (RAM Select Register) (Address: 0x104)

Bits 0~7 , FSR is used for indirect addressing to select a register(address: 00~FF).

If the user doesn’t use indirect addressing, R4 can be used as a 8-bit general purpose read-write register.

P5 (Port 5 Register) (Address: 0x105)

While IOC5 is setup as input, and ACHEN=1 (in ADC_CON), CHS3~CHS0 are analog inputs, otherwise are general purpose I/O ports

P6 (Port 6 Register) (Address: 0x106)

While SPI2 is enabled, P65-P62 are used for SPI function; While  UART is enabled, P67-P66 are used as serial port, otherwise as general purpose I/O ports

P7 (Port 7 Register) (Address: 0x107)

While ADC reference voltage input is enabled, P70 is ADC reference voltage input, the voltage must less than 3.6V, otherwise P70 is general purpose I/O port

P8 (Port 8 Register) (Address: 0x108)

While IOC8 is setup as input, and ACHEN=1(in ADC_CON), CHS3~CHS0 are analog inputs; While DA is enabled, P86 is DA output, otherwise it is general purpose I/O port

P9 (Port 9 Register) (Address: 0x109)

While SPI is enable, P95-P92 are used for SPI function; While PWM is enable, P91-P90 are used for PWM function, otherwise are general purpose I/O ports

CONTW (Write control register) (Address: 0x122)

CONTR (Read control register) (Address: 0x124)

CONTW is a writable register, and CONTR is a readable register, includes setup bit of TMR0 frequency prescaler and WDT frequency scaler(can be arranged register solely, called prescaler,too), and other control bits such as pull-high function of external interrupt and I/O ports

Ex.: To get 1:1 prescale for TMR0, the user can assign the prescaler to WDT.

/PHEN: P6、P9 Pull-High Enable

              1: Disable pull-high

              0: Enable pull-high

/INT:  Interrupt Enable

1: Enable interrupt by instruction ENI/RETI

0: Disable interrupt by instruction DISI

PAB:  Prescaler Assign

1: Assign prescaler to WDT

0: Assign prescaler to Timer0

PSR2-0:  TCC/WDT Prescaler setup

IOC5 (P5 port control register) (Address: 0x125)

“1”: I/O is defined as input;

”0”: I/O is defined as output

IOC6 (P6 port control register) (Address: 0x126)

“1”: I/O is defined as input;

”0”: I/O is defined as output

IOC7 (P7 port control register) (Address: 0x127)

“1”: I/O is defined as input;

”0” I/O is defined as output

IOC8 (P8 port control register) (Address: 0x128)

“1”: I/O is defined as input;

”0”: I/O is defined as output

IOC9 (P9 port control register) (Address: 0x129)

“1”: I/O is defined as input;

”0”: I/O is defined as output

IOC5, IOC6, IOC7, IOC8, IOC9, IOCA: all reset to 1

T1CON (Timer1 Control Register) (Address: 0x12C)

TM1E:  TIMER1 Enable

0: Disable timer1

1: Enable timer1

TM1P1-0:  TIMER1 Frequency Prescaler Setup（prescale for Fosc/2）

PULL_HIGH (Pull High Control Register) (Address: 0x12D)

Pull-high enable control.

 0: Enable

1: Disable.

Port 6, port 9 pull-high is enabled or disabled by the result of /PU6、/PU9 AND with /PHEN

S7: Setup S7 to change the ability of sink current on P70-P73

       1: Boost up the ability of sink current on P70-P73

       0: P70-P73 has normal ability of sink current

/PUA: Setup the pull-low resisters of PA0-PA2 and pull-high resisters of PA3-PA5

       1: Cut off the pull-low resisters of PA0-PA2 and pull-high resisters of PA3-PA5

       0: Connect the pull-low resisters of PA0-PA2 and pull-high resisters of PA3-PA5

/PU7: Setup the internal pull-high resisters (2k) of P74 and P75

       1: Cut off the internal pull-high resisters (2k) of P74 and P75

       0: Connect the internal pull-high resisters (2k) of P74 and P75

/PU9: Setup the pull-high resisters of P9

       1: Cut off the pull-high resisters of P9

       0: Connect the pull-high resisters of P9

/PU8: Setup the pull-high resisters of P8

       1: Cut off the pull-high resisters of P8

       0: Connect the pull-high resisters of P8

/PU6: Setup the pull-high resisters of P6

       1: Cut off the pull-high resisters of P6

       0: Connect the pull-high resisters of P6

/PU5: Setup the pull-high resisters of P5

       1: Cut off the pull-high resisters of P5

       0: Connect the pull-high resisters of P5

WDTCON (WDT Control Register) (Address: 0x12E)

ODE: Open-Drain Control

           0: P76, P77 are general purpose I/O pins

           1: P76, P77 are open drain outputs

WDTE: WDT Enable, only works while ENWDT =1 (in OPTION CODE)

           0: WDT Disable

           1: WDT Enable

WDT control. WDTE is invalid when ENWDT=0. It is said that while ENWDT=0,WDT can’t be enabled no matter what WDTE is. So WDTE is valid only while ENWDT=1. While ENWDT=1, WDT can be enable or disable by WDTE setup, 0=WDT enable， 1=WDT disable.  WDTE is a read-write bit.

SLPC: SLEEP2 mode control, clear this bit to enter SLEEP2 mode.

This bit can be set to be 1 by a wake-up signal produced by hardware, and can be cleared by software. SLPC is used to control oscillator, too. If it changes from high to low, the oscillator will stop (when oscillator stops, CPU enter SLEEP2 mode). If SLPC changes from low to high, the oscillator will start to work (CPU is waked up from SLEEP2 mode). To ensure the oscillator works stably, there is must a delay more than 18ms after waking up the oscillator. OST is activated while CPU is waked up from SLEEP2 mode, it will start to work no matter ENWDT=0 or 1. If ENWDT=1, WDT will be valid after waking up. SLPC is readable and writable.

/WUEA: Wake-Up by PA Enable

           0: Wake up MCU by PA0~PA2 is allowed

           1: Wake up MCU by PA0~PA2 is not allowed

/WUE9: Wake-Up by P9 Enable

           0: Wake up MCU by P90~P92 is allowed

           1: Wake up MCU by P90~P92 is not allowed

/WUE7: Wake-Up by P7 Enable

           0: Wake up MCU by P74~P75 is allowed

           1: Wake up MCU by P74~P75 is not allowed

/WUE6: Wake-Up by P6 Enable

           0: Wake up MCU by P60~P67 is allowed

           1: Wake up MCU by P60~P67 is not allowed

INTIE (Interrupt Enable Register)  (Address: 0x12F)

       INTIE is a readable and writable register. It contains enable bits for TMR0 time-out, external interrupt (INT)on falling edge, SPI and SPI2 interrupts, and TMR1 matching interrupt.

SPI2IE: SPI2 Interrupt Enable

           0: Disable SPI2 interrupt

           1: Enable SPI2 interrupt

TM1IE: TIMER1 Interrupt Enable

           0: Disable TIMER1 and PWP matching interrupt  

           1: Enable TIMER1 and PWP matching interrupt 

SPIIE: SPI Interrupt Enable

           0: Disable SPI interrupt

           1: Enable SPI interrupt

EXIE: External Interrupt Enable

           0: Disable external interrupt

           1:Enable external interrupt

TCIE: TCC Interrupt Enable

           0: Disable TCC time-out interrupt

           1: Enable TCC time-out interrupt

PWM1_DC  (PWM1 Duty Ratio Register)  (Address: 0x130)

Duty Cycle = (PWM_DC/PWM_PR)*100％

PWM2_DC (PWM2 Duty Ratio Register)  (Address: 0x131)

PWM1_PR (PWM1 Period Register)  (Address: 0x132)

PWM2_PR (PWM2 Period Register)  (Address: 0x133)

PWMCON (PWM Control Register)  (Address: 0x134)

The three registers above are not readable, and instructions such as BS, BC, JBS, JBC are prohibited to use to them.

PE2-1:  PWM1 and PWM2 control bit. PE2-1=1: PWM enable

PS2[2:0]/PS1[2:0] :  PWM prescale

PWM calculation:

       PWM frequency = (Oscillation Frequency / PWM Clock / PWMI_PR

       Duty Ratio = (PWMI_DC / PWMI_PR) * 100%

       Example: Oscillation Frequency = 455 KHz PS2 [2:0] (Prescale) = 000 (clock = Fosc/2)

       PWMI_PR = 6    PWMI_DC = 2

       PWM frequency = 455K / 2 / 6 = 37.9 KHz

       Duty Ratio = 2 / 6 * 100% = 33.3%

SPIRB (SPI Read Buffer)  (Address: 0x13A)

   8-bit data received is put into read buffer.

SPIWB (SPI Write Buffer)  (Address: 0x13B)

   8-bit data to be transmitted is put into write buffer.

SPIS (SPI Status Register)  (Address: 0x13C)

       TIMR1IF: TIMER1 Interrupt Flag

              1: TIMER1 interruption occurred

              0: No TIMER1 interruption occurred

       OD3: Open Drain Control

              1: SDO is set as open drain output

              0: SDO isn’t set as open drain output

       OD4: Open Drain Control

              1: SCK is set as open drain output

              0: SCK isn’t set as open drain output

       RBFIF: Read Buffer Full Interrupt Flag

              1: Receiving completed, SPIB buffer is full, and interruption occurred

              0: Receiving is not completed, SPIB buffer is empty

       RBF: Receive Buffer Full Flag

              1: Receiving completed, SPIB buffer is full

              0: Receiving is not completed, SPIB buffer is empty

SPIC  (SPI Control Register)  (Address: 0x13D)

CES: Clock Edge Selection

1: Shift-out data at falling edge, shift-in data at rising edge, and holding data while high level

0: Shift-out data at rising edge, shift-in data at falling edge, and holding data while low level

SPIE: SPI Enable

1: Enable SPI

0: Disable SPI

SRO: SPI Buffer Overflow Flag

1: Old data has not been read while new data is loading. Only valid in slave mode.

0: Old data has been read while new data is loading. Only valid in slave mode.

SSE: SPI Shift Enable.

    Start to shift-out data when set to 1, clear by hardware after shifting 

ORD: Data Transmit Order

       1: Lower bit first

       0: Higher bit first

SBRS2-0: SPI Baud Rate Selection

TMR1(TIMER1 Register)  (Address: 0x13E)

This register is TIMER1’s counter, and the value will restart from 00 when it is equal to PWP.

PWP (Pulse Width Preset Register)  (Address: 0x13F)

The desired width of baud clock is written to PWP in advance.

ADCON  (AD Control Register)  (Address: 0x140)

   ADC: AD Convert Complete Flag

         0: Clear by hardware after AD converting

         1: Set to 1 by software to enable AD converting

 ADEN: ADC Enable

         0: Disable AD

         1: Enable AD

   ACHEN: Channel Input Enable

         0: Disable CH8~CH15(P80~P87) channel input

         1: Enable CH8~CH15(P80~P87) channel input

CHS3  CHS2  CHS1  CHS0 : Analog Channel Selection

0      0      0      0  :  no use

0      0      0      1  :  AD1（P51）

0      0      1      0  :  AD2（P52）

0      0      1      1  :  AD3（P53）

0      1      0      0  :  AD4（P54）

0      1      0      1  :  AD5（P55）

0      1      1      0  :  AD6（P56）

0      1      1      1  :  AD7（P57）

1      0      0      0  :  AD8（P80）

1      0      0      1  :  AD9（P81）

1      0      1      0  :  AD10（P82）

1      0      1      1  :  AD11（P83）

1      1      0      0  :  AD12（P84）

1      1      0      1  :  AD13（P85）

1      1      1      0  :  AD14（P86）

1      1      1      1  :  AD15（P87）

AD_LSB  (Least Significant 2 Bits of AD) (Address: 0x141)

The Least Significant 2 Bits of AD result

AD_MSB  (Most Significant 8 bits of AD) (Address: 0x142)

The Most Significant 8 Bits of AD result

ADCON2  (AD Control Register)  (Address: 0x143)

VREF_IN: ADC Reference Voltage Selection

          0: Use internal LDO as reference voltage

          1: Use voltage on P70 as reference voltage, and it must be less than 3.6V

ADPS[2:0]: ADC Clock Selection

ACHCON  (AD Channel Control Register) (Address:0x17A)

ACHEN7：CH7 channel input

         0：Disable CH7(P57) channel input

         1：Enable CH7(P57) channel input

ACHEN6：CH6 channel input

         0：Disable CH6(P56) channel input

         1：Enable CH6(P56) channel input

ACHEN5：CH5 channel input

         0：Disable CH5(P55) channel input

         1：Enable CH5(P55) channel input

ACHEN4：CH4 channel input

         0：Disable CH4(P54) channel input

         1：Enable CH4(P54) channel input

ACHEN3：CH3 channel input

         0：Disable CH3(P53) channel input

         1：Enable CH3(P53) channel input

ACHEN2：CH2 channel input

         0：Disable CH2(P52) channel input

         1：Enable CH2(P52) channel input

ACHEN1：CH1 channel input

         0：Disable CH1(P51) channel input

         1：Enable CH1(P51) channel input

PA (Port A)  (Address: 0x148)

One general purpose register for I/O

IOCA (I/O A Control Register)  (Address: 0x149)

1:  Set the I/O as input

0:  Set the I/O as output

PAL (Low 8 bits of Table Pointer)  (Address: 0x14B)

PAH (High 8 bits of Table Pointer)  (Address: 0x14C)

This method for looking up table could be used with no limit in any place of program memory. The table pointer must be set in advance. Do as this: put the low 7 bits of table address into PAL[7:1] . PAL[0] is used to define the high or low byte of table, if PAL[0]=0, it is low byte, otherwise is high byte. Put the high 6 bits address into PAH[5:0] . Then the data in table can be read by “MOVC” instruction from the memory that addressed by [PAH, PAL]

Example:

CODE_TAB:

       MOV             PAL, A                                   ; Move the offset into PAL

       MOV             A, @((CODE_TAB_DB << 1 )& 0X00FF)   ;Get the low 7 bits of table pointer

; address, and put them into PAL[7:1]

       ADD              PAL, A                                       ; Add with the offset, and put the result into PAL

       MOV             A, @(CODE_TAB_DB >> 7)                     ;Get high 6 bits of table pointer address

       MOV             PAH, A          ; put into PAH

       MOVC                                ;Read data

       RET

CODE_TAB_DB:                                                ; Low 8 bits data in front

      DB         0X014, 0X00F              ; K1, K2

      DB         0X00B, 0X00C             ; K3, K4

      DB         0X00E, 0X016              ; K5, K6

      DB         0X000, 0X001              ; K7, K8

DACON  (DA Control Register)  (Address: 0x14D)